Careers

Silicon

Founding Silicon Engineer

Design model-specific inference hardware from performance modeling through RTL and verification.

Location
Cambridge
Office
Mon, Wed, Fri
Compensation
Top-of-market compensation + significant equity

About Gradiated

  1. Gradiated is a research lab focused on inference. We co-design software and hardware for efficiently serving open-weight models.
  2. Our goal is to maximize intelligence per joule. We work across model behavior, software, systems, and silicon to find better ways to run models.
  3. We start by thinking about the model as a mathematical function, and map that out onto hardware and then build software on top of that which is custom to each model. This maximises performance and removes wasted abstractions.
  4. We are early. You will help set the technical direction and the way the company works.

Why this role exists

  1. This role will be part of our initial silicon team. The team will explore architectures for our inference workloads and turn the selected designs into working silicon.
  2. You will own a substantial part of the design and follow it through performance modeling, microarchitecture, RTL, and verification. You do not need to be an expert in every area, but you must work across the interfaces around your design.

What you will do

  1. Work with the inference research team to turn workload measurements into design requirements.
  2. Build analytical and cycle-accurate models to compare compute units, numerical formats, memory systems, dataflows, and interconnects.
  3. Own one or more design areas from microarchitecture through RTL implementation.
  4. Write test plans, build verification environments, and close functional and performance coverage.
  5. Use power, performance, area, and verification results to revise the design.
  6. Define hardware-software interfaces and the low-level execution model with the inference research team.
  7. Automate architecture exploration, simulation, regression testing, and analysis.
  8. Support emulation, tape-out, and silicon bring-up as the program advances.

Problems you may work on

  1. Compute units and numerical formats for target model operations.
  2. Memory hierarchies for weights, activations, and KV-cache state.
  3. Sparse access, expert routing, and data movement.
  4. On-chip and chip-to-chip communication for model parallelism.
  5. Performance models that stay useful as the design changes.
  6. Verification strategies for long-running and highly parallel model workloads.

What we are looking for

  1. You have deep experience in at least one area: microarchitecture, performance modeling, RTL design, or design verification.
  2. You can work across the adjacent parts of architecture, RTL, verification, and software.
  3. You can write SystemVerilog and use Python or C++ for modeling, automation, and verification.
  4. You understand pipelines, memory systems, interconnects, and ASIC design flows.
  5. You can turn incomplete workload evidence into a testable design question.
  6. You use measured results to explain technical trade-offs.
  7. Tape-out or silicon bring-up experience is useful, but it is not required for every candidate.

This role is not for you if

  1. You want a narrowly specified block with fixed interfaces.
  2. You only want to focus on hardware, and are not interested in understanding models.
  3. You want to hand issues to another team when they cross a design boundary.
  4. You need a clear specification before you can start.

How we work

  1. We like to experiment a lot and do the hard thing even if it's likely to fail.
  2. We work in the office on Monday, Wednesday, Friday. We value working in person to solve hard problems, but are also flexible, some of the team work abroad for short periods.

Pay and equity

  1. We offer top-of-market compensation, with significant equity.
  2. We pay at the top of the market because talent density is what allows us to build the most efficient inference. We want a small team of exceptional people who have fun solving hard problems together.

Interview process

  1. A 60-minute call about your goals and the role.
  2. We get together in person and talk through the problems we will work on.
  3. A paid in-person working session, so we can get to know you and you can meet the team.
  4. References and an offer decision.

Apply

Let's talk.

If this sounds interesting to you, we'd like to hear from you. Fill in the form below and we'll get back to you within a few days.

Loading the application form

Gradiated is a brand owned by PostHog.

© 2026 PostHog Inc.

Cambridge, --:--:-- GMT